LM27402 datasheet(12/32 Pages) NSC

12 / 32 page

30092622

FIGURE 2. Current Limit Timing Diagram

In the example shown in Figure 2, the LM27402 immediately

turns off the high-side FET when an over-current pulse is de-

tected. After the third over-current event is detected, 24

switching cycles occur before the fourth over-current pulse is

detected. Since the current limit logic does not count 32

switching cycles between two over-current events, the inter-

nal current limit counter is not reset and continues counting

until the LM27402 enters hiccup mode. The soft-start capac-

itor is then discharged to initialize startup and a wait period of

1.28 ms occurs.

NEGATIVE CURRENT LIMIT

To prevent excess negative current, the LM27402 imple-

ments a negative current limit through the low-side FET.

Negative current limit is only enabled when an over-voltage

event is detected. Should an over-voltage fault occur, the low-

side FET will turn off if the SW pin voltage exceeds a positive

100mV during the low-side on time, thereby protecting the

powertrain from excessive negative current.

POWER GOOD

The PGOOD pin of the LM27402 is used to signal when the

output is out of regulation or during non-regulated pre-biased

conditions. This means that current limit, UVLO, over-voltage

threshold, under-voltage threshold, or a non regulated output

will cause the PGOOD pin to pull low. To prevent glitches to

PGOOD, a 20

μs de-glitch filter is built into the LM27402.

Figure 3 illustrates when the PGOOD flag is asserted low.

LM27402 Datenblatt(PDF) 12 Page - National Semiconductor (TI)