33480 datasheet(17/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33480

FUNCTIONAL DESCRIPTION

FUNCTIONAL TERMINAL DESCRIPTION

IGNITION INPUT (IGN)

The ignition input wakes the device. It also controls the Fail

mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

FLASHER INPUT (FLASHER)

The flasher input wakes the device. It also controls the Fail

Mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

RESET INPUT (RSTB)

This input wakes the device when the RSTB terminal is at

logic [1]. It is also used to initialize the device configuration

and the SPI faults registers when the signal is low. All SI/SO

registers described Table 8 and Table 11 are reset. The fault

management is not affected by RSTB (see Figure 2).

CURRENT SENSE OUTPUT (CSNS)

The current sense output terminal is an analog current

output. The routing to the external resistor is SPI

programmable.

CHARGE PUMP (CP)

An external capacitor is connected between this terminal

and VBAT terminal. It is used as a tank for the internal charge

pump. Its value is 100 nF ±20%, 25V maximum.

FETOUT OUTPUT (FETOUT)

This output terminal is used to control an external

MOSFET (OUT6).

The high level of the FETout Output is Vcc if Vbat and Vcc

are available in case of FETout is controlled ON.

FETout is not protected in case of short circuit or

undervoltage on Vbat.

In case of reverse battery, OUT6 is OFF.

FETIN INPUT (FETIN)

This input terminal gives the current recopy of the external

MOSFET. It can be routed on CSNS output by SPI command.

SPI PROTOCOL DESCRIPTION

The SPI interface has a full-duplex, three-wire

synchronous data transfer with four I/O lines associated with

it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),

and Chip Select (CS).

The SI/SO terminals of the 33480 device follow a first-in,

first-out (D15 to D0) protocol, with both input and output

words transferring the most significant bit (MSB) first. All

inputs are compatible with 5.0 V CMOS logic levels, supplied

by Vcc.

The SPI lines perform the following functions:

SERIAL CLOCK (SCLK)

The SCLK terminal clocks the internal shift registers of the

33480 device. The SI terminal accepts data into the input shift

terminal shifts data information out of the SO line driver on

the rising edge of the SCLK signal. It is important that the

SCLK terminal be in a logic low state whenever CS makes

any transition. For this reason, it is recommended the SCLK

terminal be in a logic [0] whenever the device is not accessed

(CS logic [1] state). SCLK has an internal pulldown, IDWN.

When CS is logic [1], signals at the SCLK and SI terminals

are ignored and SO is tri-stated (high impedance) (see

Figure 6).

Figure 6. Single 16-Bit Word SPI Communication

CSB

SCLK

D15

D14

D13

D12

D11

D10

OD12

OD13

OD14

OD15

OD6

OD7

OD8

OD9

OD10

OD11

OD1

OD2

OD3

OD4

OD5

RSTB is in a logic H state during the above operation.

DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC

NOTES:

OD0

device.

1. D15 : D0 relate to the most recent ordered entry of data into the device.

2. OD15 : OD0 relate to the first 16 bits of ordered fault and status data out of the device.

Notes

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