MCP3901 datasheet(27/62 Pages) MICROCHIP

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DS22192D-page 27

MCP3901

5.5

SINC3 Filter

Both ADCs present in the MCP3901 include a

decimation filter that is a third-order sinc (or notch)

filter. This filter processes the multi-bit bitstream into

16 or

24-bit

words

(depending

the

WIDTH

Configuration bit). The settling time of the filter is

3 DMCLK periods. It is recommended that unsettled

data be discarded to avoid data corruption, which can

be done easily by setting the DR_LTY bit high in the

STATUS/COM register.

The resolution achievable at the output of the sinc filter

(the output of the ADC) is dependant on the OSR and

is summarized with the following table:

For 24-Bit Output mode (WIDTH = 1), the output of the

sinc filter is padded with least significant zeros for any

resolution less than 24 bits.

For 16-Bit Output modes, the output of the sinc filter is

rounded to the closest 16-bit number in order to

conserve only 16-bit words and to minimize truncation

error.

The gain of the transfer function of this filter is 1 at each

multiple of DMCLK (typically 1 MHz) so a proper

anti-aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

converter. This anti-aliasing filter can be a simple,

first-order RC network with a sufficiently low time

constant to generate high rejection at DMCLK

frequency.

EQUATION 5-1:

SINC FILTER TRANSFER

FUNCTION H(Z)

Where:

The Normal Mode Rejection Ratio (NMRR) or gain of

the transfer function is given by the following equation:

EQUATION 5-2:

MAGNITUDE OF

FREQUENCY RESPONSE

H(f)

or:

where:

Figure 5-3 shows the sinc filter frequency response:

FIGURE 5-3:

SINC Filter Response with

MCLK = 4 MHz, OSR = 64, PRESCALE = 1.

TABLE 5-3:

ADC RESOLUTION vs. OSR

OSR<1:0>

OSR

ADC Resolution (bits)

No Missing Codes

128

256

()

OSR

–

OSR 1

–

()

---------------------------------

⎝⎠

⎜⎟

⎛⎞ 3

πfj

DMCLK

----------------------

⎝⎠

⎛⎞

exp

NMRR f

()

DMCLK

----------------------

⋅

⎝⎠

⎛⎞

sin

DRCLK

--------------------

⋅

⎝⎠

⎛⎞

sin

----------------------------------------------

NMRR f

()

π f

----

⋅

⎝⎠

⎛⎞

sin

π f

-----

⋅

⎝⎠

⎛⎞

sin

-----------------------------

()

sin

()

sin

---------------

-120

-100

-80

-60

-40

-20

100

1000

10000

100000 1000000

Input Frequency (Hz)

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