MCP3901 datasheet(17/62 Pages) MICROCHIP

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DS22192D-page 17

MCP3901

3.11

Oscillator and Master Clock Input

Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock for the

device. When CLKEXT = 0 (default), a resonant crystal

or clock source with a similar sinusoidal waveform must

be placed across these pins to ensure proper

operation. The typical clock frequency specified is

4 MHz. However, the clock frequency can be 1 MHz to

5 MHz without disturbing ADC accuracy. With the

current boost circuit enabled, the master clock can be

used up to 8.192 MHz without disturbing ADC

accuracy. Appropriate load capacitance should be

connected to these pins for proper operation.

3.12

CS (Chip Select)

This pin is the SPI chip select that enables the serial

communication.

When

this

high,

communication can take place. A chip select falling

edge initiates the serial communication and a chip

select rising edge terminates the communication. No

communication can take place, even when CS is low

and when RESET is low.

This input is Schmitt triggered.

3.13

SCK (Serial Data Clock)

This is the serial clock pin for SPI communication.

Data is clocked into the device on the rising edge of

SCK. Data is clocked out of the device on the falling

edge of SCK.

The MCP3901 interface is compatible with both SPI 0,0

and 1,1 modes. SPI modes can only be changed during

a Reset.

The maximum clock speed specified is 20 MHz when

DVDD > 4.5V and 10 MHz otherwise.

This input is Schmitt triggered.

3.14

SDO (Serial Data Output)

This is the SPI data output pin. Data is clocked out of

the device on the falling edge of SCK.

This

stays

high-impedance during the first

command byte. It also stays high-impedance during the

whole communication for write commands, and when

the CS pin is high or when the RESET pin is low. This

pin is active only when a read command is processed.

Each read is processed by a packet of 8 bits.

3.15

SDI (Serial Data Input)

This is the SPI data input pin. Data is clocked into the

device on the rising edge of SCK.

When CS is low, this pin is used to communicate with a

series of 8-bit commands.

The interface is half-duplex (inputs and outputs do not

happen at the same time).

Each communication starts with a chip select falling

edge, followed by an 8-bit command word entered

through the SDI pin. Each command is either a read or

a write command. Toggling SDI during a read

command has no effect.

This input is Schmitt triggered.

Note:

When CLKEXT = 1, the crystal oscillator is

disabled, as well as the OSC2 input. The

OSC1 becomes the master clock input,

CLKI, the direct path for an external clock

source; for example, a clock source

generated by an MCU.

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