LPC1850 datasheet(67/157 Pages) PHILIPS

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LPC1850_30_20_10

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Preliminary data sheet

Rev. 3 — 6 December 2011

67 of 157

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-CODE bus,

and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and

data accesses from different slave ports.

The LPC1850/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M3

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slave ports of the matrix to be

accessed simultaneously by different bus masters.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual.

LPC1850 Datenblatt(PDF) 67 Page - NXP Semiconductors