HT46R92 datasheet(28/61 Pages) HOLTEK

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HT46R92

Rev. 1.10

November 5, 2008

fSYS

A/D Clock Period (tAD)

ADCS2, ADCS1,

ADCS0=000

(fSYS/2)

ADCS2, ADCS1,

ADCS0=001

(fSYS/8)

ADCS2, ADCS1,

ADCS0=010

(fSYS/32)

ADCS2, ADCS1,

ADCS0=011

1MHz

ms8ms32ms

Undefined

2MHz

ms4ms16ms

Undefined

4MHz

500ns*

ms8ms

Undefined

8MHz

250ns*

ms4ms

Undefined

A/D Clock Period Examples

Although the A/D clock source is determined by the sys-

tem clock fSYS, and by bits ADCS1 and ADCS0, there are

some limitations on the maximum A/D clock source speed

that can be selected. As the minimum value of permissible

A/D clock period, tAD,is0.5

ms, care must be taken for sys-

tem clock speeds in excess of 4MHz. For system clock

speeds in excess of 4MHz, the ADCS1 and ADCS0 bits

should not be set to

²00². Doing so will give A/D clock peri-

ods that are less than the minimum A/D clock period which

may result in inaccurate A/D conversion values. Refer to

the accompanying table for examples, where values

marked with an asterisk * show where, depending upon

the device, special care must be taken, as the values may

be less than the specified minimum A/D Clock Period.

A/D Input Pins

All of the A/D analog input pins are pin-shared with the

I/O pins on Port B. Bits PCR2~PCR0 in the ADCR regis-

ter, not configuration options, determine whether the in-

put pins are setup as normal Port B input/output pins or

whether they are setup as analog inputs. In this way, pins

can be changed under program control to change their

function from normal I/O operation to analog inputs and

vice versa. Pull-high resistors, which are setup through

configuration options, apply to the input pins only when

they are used as normal I/O pins, if setup as A/D inputs

the pull-high resistors will be automatically disconnected.

Note that it is not necessary to first setup the A/D pin as

an input in the PBC port control register to enable the A/D

input as when the PCR2~PCR0 bits enable an A/D input,

the status of the port control register will be overridden.

The A/D reference voltage is supplied on an individual

VREF pin and can be connected to an external reference

voltage source. Appropriate measures should be taken to

ensure that the VREF voltage does not exceed the VDD

voltage level and that it remains as stable and noise free

as possible.

Initialising the A/D Converter

The internal A/D converter must be in a special way.

Each time the Port B A/D channel selection bits are modi-

fied by the program, the A/D converter must be

re-initialised. If the A/D converter is not initialised after the

channel selection bits are changed, the EOCB flag may

have an undefined value, which may produce a false end

of conversion signal. To initialise the A/D converter after

the channel selection bits have changed, then, within a

time frame of one to ten instruction cycles, the START bit

in the ADCR register must first be set high and then im-

mediately cleared to zero. This will ensure that the EOCB

flag is correctly set to a high condition.

A C S R R e g i s t e r

S e l e c t A / D c o n v e r t e r c l o c k s o u r c e

N o t i m p l e m e n t e d , r e a d a s " 0 "

A / D O n / O f f c o n t r o l

1 : o f f

0 : o n

F o r t e s t m o d e u s e o n l y

b 0

A D C S 1 A D C S 0

A D C S 1

A D C S 0

: s y s t e m c l o c k / 2

: s y s t e m c l o c k / 8

: s y s t e m c l o c k / 3 2

: u n d e f i n e d

: s y s t e m c l o c k

: s y s t e m c l o c k / 4

: s y s t e m c l o c k / 1 6

: u n d e f i n e d

b 7

T E S T A D O N B

A D C S 2

A/D Converter Clock Source Register

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