ADS5500MPAPREP datasheet(28/36 Pages) TI1

28 / 36 page

ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

www.ti.com

For high input frequency sampling, it is recommended

to use a clock source with very low jitter. Additionally,

the internal ADC core uses both edges of the clock for

the conversion process. This means that, ideally, a 50%

duty cycle should be provided. Figure 13 shows the

performance variation of the ADC versus clock duty

cycle.

SFDR

SNR

Clock Duty Cycle (%)

S =125MSPS

IN =20MHz

Figure 13. AC Performance vs Clock Duty Cycle

Bandpass filtering of the source can help produce a

50% duty cycle clock and reduce the effect of jitter.

When using a sinusoidal clock, the clock jitter further

improves as the amplitude is increased. In that sense,

using a differential clock allows for the use of larger

amplitudes without exceeding the supply rails and

absolute maximum ratings of the ADC clock input.

Figure 14 shows the performance variation of the

device versus input clock amplitude. For detailed

clocking schemes based on transformer or PECL-level

clocks,

see

the

ADS5500EVM

user’s

guide

(SLWU010), available for download from www.ti.com.

AC PERFORMANCE vs CLOCK AMPLITUDE

Differential Clock Amplitude (V)

S =125MSPS

IN =70MHz

0.5

1.0

1.5

2.0

2.5

3.0

SFDR

SNR

Figure 14. AC Performance vs Clock Amplitude

INTERNAL DLL

In order to obtain the fastest sampling rates achievable

with the ADS5500, the device uses an internal digital

phase lock loop (DLL). Nevertheless, the limited

frequency range of operation of DLL degrades the

performance at clock frequencies below 60 MSPS. In

order to operate the device below 60 MSPS, the internal

DLL must be shut off using the DLL OFF mode

described in the Serial Interface Programming section.

The

Typical

Performance

Curves

show

the

performance obtained in both modes of operation − DLL

ON (default) and DLL OFF. In either of the two modes,

the device enters power-down mode if no clock or a

slow clock is provided. The limit of the clock frequency

where the device functions properly is ensured to be

over 10 MHz.

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