ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

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12

PIN ASSIGNMENTS

TERMINAL

NO.

NAME

NO.

OF PINS

I/O

DESCRIPTION

AVDD

5, 7, 9, 15, 22, 24, 26,

28, 33, 34, 37, 39

12

I

Analog power supply

AGND

6, 8, 12, 13, 14, 16, 18,

21, 23, 25, 27, 32, 36, 38

14

I

Analog ground

DRVDD

49, 58

2

I

Output driver power supply

DRGND

1, 42, 48, 50, 57, 59

6

I

Output driver ground

INP

19

1

I

Differential analog input (positive)

INM

20

1

I

Differential analog input (negative)

REFP

29

1

O

Reference voltage (positive), 0.1-

µF capacitor in series with a 1-Ω

resistor to GND

REFM

30

1

O

Reference voltage (negative), 0.1-

µF capacitor in series with a

1-

Ω resistor to GND

IREF

31

1

I

Current set, 56-k

Ω resistor to GND, do not connect capacitors

CM

17

1

O

Common-mode output voltage

RESET

35

1

I

Reset (active high), 200-k

Ω resistor to AVDD

OE

41

1

I

Output enable (active high)

DFS

40

1

I

Data format and clock out polarity select(1)

CLKP

10

1

I

Data converter differential input clock (positive)

CLKM

11

1

I

Data converter differential input clock (negative)

SEN

4

1

I

Serial interface chip select

SDATA

3

1

I

Serial interface data

SCLK

2

1

I

Serial interface clock

D0 (LSB)−D13 (MSB)

44−47, 51−56, 60−63

14

O

Parallel data output

OVR

64

1

O

Over-range indicator bit

CLKOUT

43

1

O

CMOS clock out in sync with data

NOTE: PowerPAD is connected to analog ground.

(1) The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are

listed in Table 3 on page 11.