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SST49LF040 Datenblatt(PDF) 19 Page - Silicon Storage Technology, Inc |
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SST49LF040 Datenblatt(HTML) 19 Page - Silicon Storage Technology, Inc |
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19 / 48 page ![]() Advance Information 4 Mbit LPC Flash SST49LF040 19 ©2001 Silicon Storage Technology, Inc. S71213-00-000 11/01 562 FIGURE 7: RESET TIMING DIAGRAM TABLE 14: RESET TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V Symbol Parameter Min Max Units TPRST VDD stable to Reset Low 1 ms TKRST Clock Stable to Reset Low 100 µs TRSTP RST# Pulse Width 100 ns TRSTF RST# Low to Output Float 48 ns TRST1 RST# High to LFRAME# Low 1 µs TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 µs T14.0 562 1. There will be a latency of TRSTE if a reset procedure is performed during a programming or erase operation, CLK VDD RST#/INIT# LFRAME# LAD[3:0] 562 ILL F06.0 TPRST TKRST TRSTP TRSTF TRSTE Sector-/Block-Erase or Program operation aborted TRST |
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