TUSB8040A datasheet(24/39 Pages) TI1

24 / 39 page

TUSB8020A, TUSB8040A

SLLSEA7B – MAY 2012 – REVISED AUGUST 2012

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3.4.6

Device Configuration Register

Table 3-12. Register Offset 5h

Bit No.

Reset State

Table 3-13. Bit Descriptions – Device Configuration Register

Bit

Field Name

Access

Description

Custom Serial Number Enable. When the TUSB80x0A is in I2C mode,

the TUSB80x0A loads the serial number register from the contents of the

customSernum

EEPROM. When the TUSB80x0A is in SMBUS mode, the Serial Number

registers may written by an SMBus host. This bit defaults to 0.

U1 U2 Disable. When this bit is set the TUSB8040A will not initiate or

accept any U1 or U2 requests on any port, upstream or downstream,

unless it receives or sends a Force_LinkPM_Accept LMP. After receiving

or sending an FLPMA LMP, it will continue to enable U1 and U2

according to USB 3.0 protocol until it gets a power-on reset or is

u1u2Disable

disconnected on its upstream port. This bit is loaded at the de-assertion

of reset with the value of the SDA_SMBDAT terminal. When the

TUSB8040A is in I2C mode, the TUSB8040A loads this bit from the

contents of the EEPROM. When the TUSB8040A is in SMBUS mode,

the value may be over-written by an SMBus host.

Port Indicator Status. This bit shall be loaded at the de-assertion of reset

with the value of PORTINDz_SMBA3 terminal. When the TUSB8040A is

in I2C mode, the TUSB80x0A loads this bit from the contents of the

portIndz

EEPROM. When the TUSB80x0A is in SMBUS mode, the value may be

overwritten by an SMBus host.

This bit is read-only 1 for the PFP package option.

Ganged. This bit shall be loaded at the de-assertion of reset with the

value of GANGEd_SMBA2 terminal. When the TUSB80x0A is in I2C

mode, the TUSB80x0A loads this bit from the contents of the EEPROM.

ganged

When the TUSB8040A is in SMBUS mode, the value may be overwritten

by an SMBus host.

This bit is read-only 1 for PFP package option.

Full Power Management. This bit is loaded at the de-assertion of reset

with the value of the FULLPWRMGMTz_SMBA1 terminal. When this bit

is 0, power switching and over-current detection is supported whether

bus- or self-powered. When the bit is 1 and the device is bus powered,

power switching is supported but over-current detection is not supported.

fullPwrMgmtz

When the bit is 1 and the device is self-powered over-current detection is

supported but power switching is not supported. When the TUSB80x0A

is in I2C mode, the TUSB80x0A loads this bit from the contents of the

EEPROM. When the TUSB80x0A is in SMBUS mode, the value may be

over-written by an SMBus host.

U1 U2 Timer Override. When this bit is set the TUSB80x0A will override

the downstream ports u1/u2 timeout values set by software. If software

sets a value in the range of 1-FF, the TUSB80x0A will use the value FF.

If software sets a value of 0, the TUSB80x0A will use the value 0.This bit

u1u2TimerOvr

is loaded at the de-assertion of reset with the value of the SCL_SMBCLK

terminal. When the TUSB80x0A is in I2C mode, the TUSB8040A loads

this bit from the contents of the EEPROM. When the TUSB80x0A is in

SMBUS mode, the value may be over-written by an SMBus host.

RSVD

Reserved. Read only, returns 0 when read.

FUNCTIONAL DESCRIPTION

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