TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE

TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE

SMMS660 – MARCH 1996

7

POST OFFICE BOX 1443

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (continued)

’124FBK32F - 60

’248GBK32F - 60

’124FBK32F - 70

’248GBK32F - 70

’124FBK32F - 80

’248GBK32F - 80

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tRWL

Setup time, W low before RAS high

10

12

15

ns

tWCS

Setup time, W low before CAS low

0

0

0

ns

tCAH

Hold time, column address after CAS low

10

15

15

ns

tDH

Hold time, data after CAS low

10

15

15

ns

tRAH

Hold time, row address after RAS low

10

10

10

ns

tRCH

Hold time, W high after CAS high (see Note 9)

0

0

0

ns

tRRH

Hold time, W high after RAS high (see Note 9)

0

0

0

ns

tWCH

Hold time, W low after CAS low

10

15

15

ns

tRHCP

Hold time, RAS high from CAS precharge

35

40

45

ns

tCHS

Hold time, CAS low after RAS high (self refresh)

– 50

– 50

– 50

ns

tCHR

Delay time, RAS low to CAS high (CBR refresh only)

10

10

10

ns

tCRP

Delay time, CAS high to RAS low

5

5

5

ns

tCSR

Delay time, CAS low to RAS low (CBR refresh only)

5

5

5

ns

tRAD

Delay time, RAS low to column address (see Note 10)

15

30

15

35

15

40

ns

tRAL

Delay time, column address to RAS high

30

35

40

ns

tCAL

Delay time, column address to CAS high

20

25

30

ns

tRCD

Delay time, RAS low to CAS low (see Note 10)

20

45

20

52

20

60

ns

tRPC

Delay time, RAS high to CAS low (CBR only)

0

0

0

ns

tRSH

Delay time, CAS low to RAS high

10

12

15

ns

tREF

Refresh time interval

16

16

16

ms

tT

Transition time

2

30

2

30

2

30

ns

NOTES:

9. Either tRRH or tRCH must be satisfied for a read cycle.

10. The maximum value is specified only to assure access time.