CBTL06DP212

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 3 November 2011

9 of 18

NXP Semiconductors

CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

11.3 AUX and DDC ports

[1]

Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.

11.4 HPDIN input, HPD_x outputs

[1]

Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.

11.5 GPU_SEL and DDC_AUX_SEL inputs

Table 11.

AUX and DDC port characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

input voltage

0.3

-

V

output voltage

no load

-

-

V

common-mode input voltage

AUX

0

-

2.0

V

differential input voltage

AUX

-

-

+1.4

V

propagation delay

from left-side port to right-side

port or vice versa

[1] -80

-

ps

Table 12.

HPD input and output characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

input voltage

0.3

-

V

output voltage

no load

-

-

V

propagation delay

from HPDIN to HPD_x or vice versa

[1] -80

-

ps

Table 13.

GPU_SEL and DDC_AUX_SEL input characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

2.0

-

-

V

LOW-level input voltage

-

-

0.8

V

input leakage current

-

-

10

A