CBTL06DP212

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 3 November 2011

11 of 18

NXP Semiconductors

CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

13. Package outline

Fig 5.

Package outline TFBGA48 (SOT918-1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

SOT918-1

MO-195

- - -

- - -

SOT918-1

05-09-21

05-10-13

UNIT

A

max

mm

1.15

0.25

0.15

0.90

0.75

0.35

0.25

5.1

4.9

5.1

4.9

DIMENSIONS (mm are the original dimensions)

TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm

X

b

D

E

4

4

e

0.5

v

0.15

w

0.05

y

0.08

0.1

0

2.5

5 mm

scale

b

ball A1

index area

A

B

C

D

E

F

H

G

J

2468

13579

e

e

A

C

B

C

ball A1

index area

B

A

E

D

C

y

C

detail X

A