AD7660AST datasheet(14/20 Pages) AD

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REV. 0

AD7660

–14–

THROUGHPUT – SPS

100

0.01

1000

10000

100000

0.1

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion

process. The AD7660 is controlled by the signal

CNVST which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The

CNVST signal operates independently of

CS and RD signals.

For a true sampling application, the recommended operation of

the

CNVST signal is the following:

CNVST must be held high from the previous falling edge of

BUSY, and during a minimum delay corresponding to the

acquisition time t8; then, when

CNVST is brought low, a con-

version is initiated and BUSY signal goes high until the completion

of the conversion. Although

CNVST is a digital signal, it should

be designed with special care with fast, clean edges and levels,

with minimum overshoot and undershoot or ringing. For appli-

cations where the SNR is critical, the

CNVST signal should

have a very low jitter. Some solutions to achieve this are to use a

dedicated oscillator for

CNVST generation or, at least, to clock

it with a high frequency low jitter clock as shown in Figure 6.

For other applications, conversions can be automatically initi-

ated. If

CNVST is held low when BUSY is low, the AD7660

controls the acquisition phase and then automatically initiates a

new conversion. By keeping

CNVST low, the AD7660 keeps

the conversion process running by itself. It should be noted that

the analog input has to be settled when BUSY goes low. Also, at

power-up,

CNVST should be brought low once to initiate the

conversion process. In this mode, the AD7660 could sometimes

run slightly faster than the guaranteed limit of 100 kSPS.

DIGITAL INTERFACE

The AD7660 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7660 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7660

to the host system interface digital supply. Finally, by using the

OB/

2C input pin, both two’s complement or straight binary

coding can be used.

The two signals

CS and RD control the interface. CS and RD

have a similar effect because they are OR’d together internally.

When at least one of these signals is high, the interface outputs

are in high impedance. Usually,

CS allows the selection of each

AD7660 in multicircuits applications and is held low in a single

AD7660 design.

RD is generally used to enable the conversion

result on the data bus.

CNVST

BUSY

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

Figure 11. Basic Conversion Timing

RESET

DATA

BUSY

CNVST

Figure 12. RESET Timing

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