AD7660AST datasheet(15/20 Pages) AD

15 / 20 page

REV. 0

AD7660

–15–

PARALLEL INTERFACE

The AD7660 is configured to use the parallel interface when the

SER/

PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or during

the following conversion as shown, respectively, in Figure 14 and

Figure 15. When the data is read during the conversion, how-

ever, it is recommended, that it is read only during the first half

of the conversion phase. That avoids any potential feedthrough

between voltage transients on the digital interface and the most

critical analog conversion circuitry.

SERIAL INTERFACE

The AD7660 is configured to use the serial interface when the

SER/

PAR is held high. The AD7660 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin.

t11

CNVST

BUSY

DATA BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

Figure 13. Master Parallel Data Timing for Reading (Continuous Read)

CURRENT

CONVERSION

BUSY

DATA BUS

t12

t13

Figure 14. Slave Parallel Data Timing for Reading (Read after Convert)

CONVERSION

t12

t13

CS = 0

CNVST, RD

BUSY

DATA BUS

Figure 15. Slave Parallel Data Timing for Reading (Read During Convert)

MASTER SERIAL INTERFACE

Internal Clock

The AD7660 is configured to generate and provide the serial

data clock SCLK when the EXT/

INT pin is held low. The AD7660

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted if desired. The output data is valid on both the

rising and falling edge of the data clock. Depending on RDC/

SDIN input, the data can be read after each conversion, or

during the following conversion. Figure 16 and Figure 17 show

the detailed timing diagrams of these two modes.

Usually, because the AD7660 has a longer acquisition phase

than the conversion phase, the data is read immediately after

conversion. That makes the mode master, read after conver-

sion, the most recommended serial mode when it can be used.

In read-after-conversion mode, it should be noted that, unlike

in other modes, the signal BUSY returns low after the 16 data

bits are pulsed out and not at the end of the conversion phase

AD7660AST Datenblatt(PDF) 15 Page - Analog Devices

AD7660AST Datenblatt(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datenblatt Download

Link URL