AD9761ARS datasheet(12/23 Pages) AD

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AD9761

–12–

REV. A

50pF

CURRENT

SOURCE

ARRAY

+1.2V REF

REFIO

FSADJ

REFLO

COMP2

AVDD

IREF =

VREF/RSET

AVDD

RSET

EXT.

VREF

AVDD

0.1 F

AD9761

–

Figure 25. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9761 also contains an internal control amplifier which is

used to simultaneously regulate both DAC’s full-scale output

current, IOUTFS. Since the I and Q IOUTFS are derived from the

same voltage reference and control circuitry, excellent gain

matching is ensured. The control amplifier is configured as a

V-I converter as shown in Figure 25 such that its current out-

put, IREF, is determined by the ratio of the VREFIO and an exter-

nal resistor, RSET, as stated in Equation (4). IREF is copied over

to the segmented current sources with the proper scaling factor

to set IOUTFS as stated in Equation (3).

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 1 mA to 10 mA range by setting IREF between

62.5

µA and 625 µA. The wide adjustment span of I

OUTFS pro-

vides several application benefits. The first benefit relates di-

rectly to the power dissipation of the AD9761’s analog supply,

AVDD, which is proportional to IOUTFS (refer to the POWER

DISSIPATION section). The second benefit relates to the

20 dB adjustment span which may be useful for system gain

control purposes.

Optimum noise and dynamic performance for the AD9761 is

obtained with a 0.1

µF external capacitor installed between

COMP2 and AVDD. The bandwidth of the reference control

amplifier is limited to approximately 5 kHz with a 0.1

µF ca-

pacitor installed. Since the –3 dB bandwidth corresponds to the

dominant pole and hence its dominant time constant, the set-

tling time of the control amplifier to a stepped reference input

response can be easily determined. Note, the output of the

control amplifier, COMP2, is internally compensated via a

50 pF capacitor thus ensuring its stability if no external capaci-

tor is added.

Depending on the requirements of the application, IREF can be

adjusted by varying either RSET, or in the external reference

mode, by varying the REFIO voltage. IREF can be varied for a

fixed RSET by disabling the internal reference and varying the

voltage of REFIO over its compliance range of 1.25 V to 0.10 V.

REFIO can be driven by a single-supply amplifier or DAC thus

allowing IREF to be varied for a fixed RSET. Since the input im-

pedance of REFIO is approximately 1 M

Ω, a simple, low cost

R-2R ladder DAC configured in the voltage mode topology may

be used to control the gain. This circuit is shown in Figure 26

using the AD7524 and an external 1.2 V reference, the AD1580.

ANALOG OUTPUTS

As previously stated, both the I and Q DACs produce two

complementary current outputs which may be configured for

single-end or differential operation. IIOUTA and IIOUTB can be

converted into complementary single-ended voltage outputs,

VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in

the DAC TRANSFER SECTION by Equations 5 through 8.

The differential voltage, VIDIFF, existing between VIOUTA and

VIOUTB can also be converted to a single-ended voltage via a

transformer or differential amplifier configuration.

Figure 27 shows an equivalent circuit of the AD9761’s I (or Q)

DAC output. It consists of a parallel array of PMOS current

sources in which each current source is switched to either

IOUTA or IOUTB via a differential PMOS switch. As a result,

the equivalent output impedance of IOUTA and IOUTB re-

mains quite high (i.e., >100 k

Ω and 5 pF).

AD9761

AVDD

RLOAD

IOUTA

IOUTB

Figure 27. Equivalent Circuit of the AD9761 DAC Output

IOUTA and IOUTB have a negative and positive voltage com-

pliance range which must be adhered to achieve optimum per-

formance. The negative output compliance range of –1 V is set

by the breakdown limits of the CMOS process. Operation be-

yond this maximum limit may result in a breakdown of the

output stage.

50pF

CURRENT

SOURCE

ARRAY

+1.2V REF

REFIO

FSADJ

REFLO

COMP2

AVDD

AD1580

1.2V

OPTIONAL

BANDLIMITING

CAPACITOR

IREF =

VREF/RSET

AVDD

RSET

0.1V TO 1.2V

RFB

VDD

OUT1

OUT2

AGND

VREF

AD7524

DB7–DB0

–

AD9761

Figure 26. Single-Supply Gain Control Circuit

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