AD9761ARS datasheet(3/23 Pages) AD

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–3–

REV. A

AD9761

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate

MSPS

Output Settling Time (tST to 0.025%)

Output Propagation Delay (tPD)

Input Clock Cycles

Glitch Impulse

pV-s

Output Rise Time (10% to 90%)

2.5

Output Fall Time (10% to 90%)

2.5

AC LINEARITY TO NYQUIST

Signal-to-Noise and Distortion (SINAD)

fOUT = 1 MHz; CLOCK = 40 MSPS

Effective Number of Bits (ENOBs)

9.0

9.5

Bits

Total Harmonic Distortion (THD)

fOUT = 1 MHz; CLOCK = 40 MSPS

–68

–58

Spurious-Free Dynamic Range (SFDR)

fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span

Channel Isolation

fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span

dBC

DIGITAL SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V

3.5

Logic “1” Voltage @ DVDD = +3 V

2.4

Logic “0” Voltage @ DVDD = +5 V

1.3

Logic “0” Voltage @ DVDD = +3 V

0.9

Logic “1” Current

–10

+10

µA

Logic “0” Current

–10

+10

µA

Input Capacitance

Input Setup Time (tS)3

Input Hold Time (tH)2

CLOCK High

CLOCK Low

Invalid CLOCK/WRITE Window (tCINV)

NOTES

CINV is an invalid window of 4 ns duration beginning 1 ns AFTER the rising edge of WRITE in which the rising edge of CLOCK MUST NOT occur.

Specifications subject to change without notice.

"I" DATA

"Q" DATA

tCINV

DB9–DB0

DAC

INPUTS

SELECT

WRITE

CLOCK

NOTES: WRITE AND CLOCK CAN BE TIED

TOGETHER. FOR TYPICAL EXAMPLES, REFER

TO DIGITAL INPUTS AND INTERLEAVED INTERFACE

CONSIDERATION SECTION.

Figure 1. Timing Diagram

(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output,

Doubly Terminated, unless otherwise noted)

(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA unless otherwise noted)

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