ADAU1461WBCPZ-R7 datasheet(75/88 Pages) AD

75 / 88 page

ADAU1461

Rev. 0 | Page 75 of 88

R42: Jack Detect Pin Control, 16,433 (0x4031)

With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.

The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to

a defined state when the signal source becomes three-state.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

JDSTR

Reserved

JDP[1:0]

Reserved

Table 74. Jack Detect Pin Control Register

Bits

Bit Name

Description

JDSTR

JACKDET/MICIN pin drive strength.

0 = low (default).

1 = high.

[3:2]

JDP[1:0]

JACKDET/MICIN pad pull-up/pull-down configuration.

Setting

Configuration

Pull-up

Reserved

None (default)

Pull-down

R67: Dejitter Control, 16,438 (0x4036)

The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated or

bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling

and reenabling certain subsystems in the device—that is, the ADCs, serial ports, SigmaDSP core, and DACs—during operation can cause

the associated dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.

When the serial ports are in master mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports

are in slave mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output to

the next subsystem in the device. Any time that audio must pass through the ADCs, serial port, sound engine/DSP core, or DACs, the

dejitter circuit can be bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately

reactivated, without a wait period, by setting the dejitter window size to the default value of 3.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DEJIT[7:0]

Table 75. Dejitter Control Register

Bits

Bit Name

Description

[7:0]

DEJIT[7:0]

Dejitter window size.

Window Size

Core Clock Cycles

00000000

…

00000011

3 (default)

…

00000101

ADAU1461WBCPZ-R7 Datenblatt(PDF) 75 Page - Analog Devices

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