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ADAU1461WBCPZ-R7 Datenblatt(PDF) 80 Page - Analog Devices

Teilenummer ADAU1461WBCPZ-R7
Bauteilbeschribung  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  88 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADAU1461WBCPZ-R7 Datenblatt(HTML) 80 Page - Analog Devices

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ADAU1461
Rev. 0 | Page 80 of 88
R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4)
The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1,
these pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
LRGP3
BGP2
SDOGP1
SDIGP0
Table 83. Serial Data/GPIO Pin Configuration Register
Bits
Bit Name
Description
3
LRGP3
LRCLK or GPIO3 pin configuration select.
0 = LRCLK enabled (default).
1 = GPIO3 enabled.
2
BGP2
BCLK or GPIO2 pin configuration select.
0 = BCLK enabled (default).
1 = GPIO2 enabled.
1
SDOGP1
ADC_SDATA or GPIO1 pin configuration select.
0 = ADC_SDATA enabled (default).
1 = GPIO1 enabled.
0
SDIGP0
DAC_SDATA or GPIO0 pin configuration select.
0 = DAC_SDATA enabled (default).
1 = GPIO0 enabled.
R61: DSP Enable, 16,629 (0x40F5)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPEN
Table 84. DSP Enable Register
Bits
Bit Name
Description
0
DSPEN
Enables the DSP. Set this bit before writing to the parameter RAM and before setting the DSPRUN bit in
Register R62 (Address 0x40F6).
0 = DSP disabled (default).
1 = DSP enabled.
R62: DSP Run, 16,630 (0x40F6)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DSPRUN
Table 85. DSP Run Register
Bits
Bit Name
Description
0
DSPRUN
Run the DSP. Set the DSPEN bit in Register R61 (Address 0x40F5) before setting this bit.
0 = DSP off (default).
1 = run the DSP.



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