W25Q80BWSVIP datasheet(41/74 Pages) WINBOND

41 / 74 page

W25Q80BW

Publication Release Date: July 30, 2013

- 41 -

Revision J

7.2.23

Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all

1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low

nd shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The

Sector Erase instruction sequence is shown in figure 21.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done

the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase

instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase

cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of

the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is

finished and the device is ready to accept other instructions again. After the Sector Erase cycle has

finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase

instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,

BP2, BP1, and BP0) bits (see Status Register Memory Protection table).

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (20h)

High Impedance

24-Bit Address

Mode 0

Mode 3

= MSB

Figure 21. Sector Erase Instruction Sequence Diagram

W25Q80BWSVIP Datenblatt(PDF) 41 Page - Winbond