PIC24FV32KA304 datasheet(75/320 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS39995B-page 75

PIC24FV32KA304 FAMILY

TABLE 7-1:

RESET FLAG BIT OPERATION

7.1

Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 7-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

For more information, see Section 9.0 “Oscillator

Configuration”

TABLE 7-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

bit 4

WDTO:

Watchdog Timer Time-out Flag bit

= WDT time-out has occurred

= WDT time-out has not occurred

bit 3

SLEEP:

Wake-up from Sleep Flag bit

= Device has been in Sleep mode

= Device has not been in Sleep mode

bit 2

IDLE:

Wake-up from Idle Flag bit

= Device has been in Idle mode

= Device has not been in Idle mode

bit 1

BOR:

Brown-out Reset Flag bit

= A Brown-out Reset has occurred (the BOR is also set after a POR)

= A Brown-out Reset has not occurred

bit 0

POR:

Power-on Reset Flag bit

= A Power-up Reset has occurred

= A Power-up Reset has not occurred

Flag Bit

Setting Event

Clearing Event

TRAPR (RCON<15>)

Trap Conflict Event

POR

IOPUWR (RCON<14>)

Illegal Opcode or Uninitialized W Register Access

POR

CM (RCON<9>)

Configuration Mismatch Reset

POR

EXTR (RCON<7>)

MCLR Reset

POR

SWR (RCON<6>)

RESET

Instruction

POR

WDTO (RCON<4>)

WDT Time-out

PWRSAV

Instruction, POR

SLEEP (RCON<3>)

PWRSAV #SLEEP

Instruction

POR

IDLE (RCON<2>)

PWRSAV #IDLE

Instruction

POR

BOR (RCON<1>)

POR, BOR

—

POR (RCON<0>)

POR

—

DPSLP (RCON<10>)

PWRSAV #SLEEP

instruction with DSCON<DSEN> set

POR

Note:

All Reset flag bits may be set or cleared by the user software.

RCON: RESET CONTROL REGISTER(1) (CONTINUED)

Note 1:

All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

On PIC24FV32KA3xx parts only, not used on PIC24F32KA3XX.

Reset Type

Clock Source Determinant

POR

FNOSC Configuration bits

(FNOSC<10:8>)

BOR

MCLR

COSC Control bits

(OSCCON<14:12>)

WDTO

SWR

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