PIC24FV32KA304 datasheet(83/320 Pages) MICROCHIP

83 / 320 page

 2011 Microchip Technology Inc.

DS39995B-page 83

PIC24FV32KA304 FAMILY

SR: ALU STATUS REGISTER

U-0

R-0, HSC

—

DC(1)

bit 15

bit 8

R/W-0, HSC R/W-0, HSC R/W-0, HSC

R-0, HSC

R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC

IPL2(2,3)

IPL1(2,3)

IPL0(2,3)

RA(1)

N(1)

OV(1)

Z(1)

C(1)

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented:

Read as ‘0’

bit 7-5

IPL<2:0>:

CPU Interrupt Priority Level Status bits(2,3)

111

= CPU interrupt priority level is 7 (15); user interrupts disabled

110

= CPU interrupt priority level is 6 (14)

101

= CPU interrupt priority level is 5 (13)

100

= CPU interrupt priority level is 4 (12)

011

= CPU interrupt priority level is 3 (11)

010

= CPU interrupt priority level is 2 (10)

001

= CPU interrupt priority level is 1 (9)

000

= CPU interrupt priority level is 0 (8)

Note 1:

See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.

The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.

The value in parentheses indicates the interrupt priority level if IPL3 = 1.

The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

Note:

Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.

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