CS4923 datasheet(34/56 Pages) CIRRUS

34 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

covered in the CS4923/4/5/6/7/8/9 Hardware

User’s

Guide.

Application

configuration

described in the application code user’s guide for

the code being used.

6.2 Parallel Host Interface

The byte wide parallel host interface of the

CS492X supports application code download,

communication for hardware and application

configuration, compressed data input, and PCM

data input. When using either Intel or Motorola

modes, the parallel interface is implemented using

four 8-bit internal registers which are selectable

using inputs A1 and A0 as shown in table 3. Table

5 shows the individual registers and their bit

mapping.

In either the Intel or Motorola mode the INTREQ

pin can be used to interrupt the host when the DSP

has unsolicited outgoing messages to be read. For

specific details on the behavior of INTREQ in one

the

parallel

modes,

please

see

the

CS4923/4/5/6/7/8/9 Hardware User’s Guide.

6.2.1 Intel Parallel Host Mode

Intel parallel host mode is accomplished with CS,

RD, WR, A[1:0], and DATA[7:0]. Table 4 shows

the pin name, pin description and pin number of

each signal on the CS4923/4/5/6/7/8/9. RD and

WR have no effect when CS is held high.

When the DSP writes a byte to the HOSTMSG

read. To initiate a read cycle the host should drive

CS low. When CS is low, RD becomes the output

enable for DATA[7:0]. When CS and RD are low,

the contents of register address A[1:0] are driven

on the DATA[7:0] bus. The address A[1:0] must be

valid a minimum time before either CS or RD goes

low. The HOUTRDY bit of the CONTROL

HOSTMSG register.

Driving both CS and WR low begins an 8-bit write

cycle. The address A[1:0] must be valid a

minimum time before either CS or WR goes low.

On the first rising edge of CS or WR, the write

cycle ends and DATA[7:0] are latched internally

by the CS492X. Data must be held sufficiently to

satisfy the hold time as given in the timing section.

The HINBSY bit is set when the host writes the

HOSTMSG register. This bit is cleared when the

byte in the HOSTMSG register is read by the DSP.

During RESET low, all control signals have no

effect and DATA[7:0] are high impedance.

(Pin 6)

(Pin 7)

CMPDATA

8-bit compressed

data to input unit

(write only)

PCMDATA

8-bit linear PCM data

to input unit (write

only)

CONTROL

Multi-bit control regis-

ter for setup and

handshaking (R/W)

HOSTMSG

8-bit control pipe

message register

(R/W)

Table 3. Host Memory Map

Pin Name

Pin Description

Pin Number

Chip Select

Output Enable

Write Enable

INTREQ

Interrupt Request

DATA7

Data Bit 7

DATA6

Data Bit 6

DATA5

Data Bit 5

DATA4

Data Bit 4

DATA3

Data Bit 3

DATA2

Data Bit 2

DATA1

Data Bit 1

DATA0

Data Bit 0

Table 4. Intel Parallel Host Mode Pin Assignments

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