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CS4923 Datenblatt(PDF) 40 Page - Cirrus Logic

Teilenummer CS4923
Bauteilbeschribung  Multi-Channel Digital Audio Decoders
PDF  56 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4923 Datenblatt(HTML) 40 Page - Cirrus Logic

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AD6
AD4
AD5
AD3 AD2 AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK
D0
ACK
D7
D6
D5
D4
D3
D2
D1
ACK
D0
D7
D6
D5
D4
D3
D2
D1
ACK
D0
I2C Start
I2C Stop
SCCLK
SCDIO
AD6
AD4
AD5
AD3 AD2 AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK
D0
ACK
D7
D6
D5
D4
D3
D2
D1
ACK
D0
D7
D6
D5
D4
D3
D2
D1
NACK
D0
I2C Start
I2C Stop
SCCLK
SCDIO
INTREQ
Note 1
Note 2
Note 3
I2C Write Functional Timing
Note 4
Note 5
I2C Read Functional Timing
Figure 20. I
2C Timing
Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9.
2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the
host.
3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to
be transferred out of the CS4923/4/5/6/7/8/9
4. A NOACK should be sent by the host after the last byte read to indicate the end of the read
cycle.
5. INTREQ is guaranteed to stay high until the next rising edge of SCCLK (for the ACK/NACK
bit) at which point it may go low again if there is new data to be read. The condition of INTREQ
going low at this point should be treated as a new read condition and a new start condition
followed by an address byte should be sent.



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