SCA3000-D01 datasheet(27/43 Pages) VTI

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SCA3000 Series

VTI Technologies Oy

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Doc.Nr. 8257300A.07

Rev.A.07

4.2

2C Interface

2C is a 2-wire serial interface. It consists of one master device and one or more slave devices. The

master is defined as a micro controller providing the serial clock (SCL), and the slave as any

integrated circuit receiving the SCL clock from the master. The SCA3000 sensor always operates

as a slave device in master-slave operation mode. When using an SPI interface, a hardware

addressing is used (slaves have dedicated CSB signals), the I

2C interface uses a software based

addressing (slave devices have dedicated bit patterns as addresses).

The SCA3000 is compatible to the Philips I

2C specification V2.1. Main used features of the I2C

interface are:

10-bit addressing, SCA3000 I

2C device address is 0x1F1

Supports standard mode and fast mode

Start / Restart / Stop

Slave transceiver mode

Designed for low power consumption

In addition to the Philips specification, the SCA3000 I

2C interface supports multiple write and read

mode.

4.2.1

2C frame format

4.2.1.1

2C write mode

In I

2C write mode, the first 8 bits after device address define the SCA3000 internal register address

to be written. If multiple data words are transferred by the master, the register address is

decreased automatically by one (see cases 1 and 2 in Figure 10).

4.2.1.2

2C read mode

The read mode operates as described in Philips I

2C specification. I2C read operation returns the

content of the register which address is defined in I2C_RD_SEL register. So when performing the

2C read operation, the register address to be read has to be written into I2C_RD_SEL register

before actual read operation. Read operation starts from register address that has been written

earlier in I2C_RD_SEL register. Read data is acknowledged by I

2C master. Automatic read

address change depends on the selected start address (see cases 3 and 4 in Figure 10).

If address is some of registers between X_LSB

Z_MSB the register address is automatically

cycled as follows:

...

Y_MSB

Y_LSB

X_MSB

X_LSB

Z_MSB

Z_LSB

Y_MSB

Y_LSB

...

If the start address is any other register, the read address is NOT automatically incremented or

decremented (the data transfer continues from the same address.) This enables the burst read

from output ring buffer (register BUF_DATA).

4.2.1.3

Decremented register read

Decremented reading is possible only for registers X_LSB ... Z_MSB. Refer to decremented read

with SPI interface section 4.1.3.2.

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