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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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IO10PDB0V0 Datenblatt(PDF) 26 Page - Microsemi Corporation |
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IO10PDB0V0 Datenblatt(HTML) 26 Page - Microsemi Corporation |
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26 / 197 page  SmartFusion DC and Switching Characteristics 2- 14 R e v i sio n 1 2 Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software. The power calculation methodology described below uses the following variables: • The number of PLLs/CCCs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • The number of eNVM blocks used in the design • The analog block used in the design, including the temperature monitor, current monitor, ABPS, sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal oscillator • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-17 on page 2-18. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-18 on page 2-18. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-18 on page 2-18. • Read rate to the eNVM blocks The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL SoC Mode, Standby Mode, and Time Keeping Mode. PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT SoC Mode PSTAT = PDC1 + (NINPUTS * PDC7) + (NOUTPUTS * PDC8) + (NPLLS * PDC9) NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NPLLS is the number of PLLs available in the device. Standby Mode PSTAT = PDC2 Time Keeping Mode PSTAT = PDC3 Total Dynamic Power Consumption—PDYN SoC Mode PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL + PeNVM + PXTL-OSC + PRC-OSC + PAB + PLPXTAL-OSC + PMSS |
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