ML7344J datasheet(57/151 Pages) ETC2

Teilenummer	ML7344J

Bauteilbeschribung	Sub-GHz band short range wireless transceiver IC

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FEDL7344C/E/J-04

ML7344C/E/J

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(3)DCLK output method

In Data output mode 2, decoded data is output. Therefore, The DCLK output section in a output interval

changes with the coding method. DCLK output section is as follows.

In othe modes, undecoded data is input or output. DCLK is output continuously. Then, it is not depend on the

coding method.

i) Data output mode 2

ii) TX continuous input mode or RX continuous mode

iii) TX Data input mode / RX Data output mode1

Output interval

NRZ:

: 8 cycle

Manchester

:16 cycle

3 out of 6

:12 cycle

DCLK

Clock output (8 cycle)

Output interval

1 cycle=1/data rate[bps]

(*) The nuber of cycle per 1 byte

NRZ

: 8 cycle

Manchester

:16 cycle

3 out of 6

:12 cycle

DCLK

TX: The timing during transmitting

the last 2 bit SyncWord

RX: DIO_START issue

1 cycle=1/data rate[bps]

(*) The nuber of cycle per 1 byte

NRZ

: 8 cycle

Manchester

:16 cycle

3 out of 6

:12 cycle

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