GMS97C2051 datasheet(11/39 Pages) HYNIX

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8-Bit CMOS Microcontorller

GMS97C2051/L2051

HYUNDAI MicroElectonics

Programming The EPROM

The GMS97C2051/L2051 is programmed by using a

modified Quick-Pulse Programming

TM algorithm. It

differs from older methods in the value used for VPP

(programming supply voltage) and in the width and

number of the P3.2( PROG ) .

The GMS97C2051/L2051 contains two signature

bytes that can be read and used by an EPROM pro-

gramming system to identify the device. The signature

bytes identify the device as an manufactured by HME .

Table 10 shows the logic levels for reading the signa-

ture byte, and for programming the program memory,

the encryption table, and the security bits. The circuit

configuration and waveforms for quick-pulse pro-

gramming are shown in Figures 5 and Figure 8.

Figure 6 shows the circuit configuration for normal

program memory verification.

EPROM Programming and Verification

Internal Address Counter :

The GMS97C2051/L2051 contains an internal EPROM

address counter which is always set to 07FFH on the

rising edge of RST after setting P3.0 to ‘H’ and is ad-

vanced by applying continuous level transition to pin

P3.0.

Programming Algorithm :

To program the GMS97C2051/L2051, the following

sequence is recommended.

1. Power-up Sequence

Apply power between VCC and GND pins with

crystal oscillation.

Set P3.0 to ‘H’.

Set RST to GND.

With all other pins floating, wait for greater than

10ms.

2. Set pin RST to ‘H’ and pin P3.2 to ‘H’.

3. Apply the appropriate combination of ‘H’ or ‘L’

logic levels to pins P3.3, P3.4, P3.5, P3.7 to select

one of the programming operations shown in the

EPROM Programming Modes. (Table 10).

To program and verify the array

4. The P3.0 level is pulled ‘L’ and apply data for

code byte at location 0000H to P1.0 to P1.7

5. Raise RST to 12.75V to enable pr ogramming.

6. The P3.2( PROG ) is pulsed low 10 times as shown

in Figure 8. Each programming pulse is low for

100us(

±10us) and high for a minimum of 10us.

7. To verify the programmed data, lower RST from

12.75V to logic ‘H’ level and set pins P3.3 to P3.7

to the appropriate levels. Output data can be read

at the port P1 pins. At this time P3.0 should not be

changed.

8. To program a byte at the next address location,

P3.0 level transition is needed to advance the

internal address counter. Apply new data to the

port P1 pins.

9. Repeat step 5 through 8, changing data and

advancing the address counter for the entire 2K

bytes array.

Program Verify :

If lock bits LB1 and LB2 have not been programmed,

code data can be read back via port P1 pins.

1. Set the internal address counter to 07FFH by

bringing RST from ‘L’ to ‘H’

and reset the

internal address counter to 0000H by bringing P3.0

from ‘H’ to ‘L’.

2. Apply the appropriate control signals for Read

Code data to pins P3.3, P3.4, P3.5, P3.7 and read

the output data at the port P1 pins.

3. The P3.0 level transition is taken to advance the

internal address counter.

4. Read the next code data byte at the port P1 pins.

5. Repeat step 3 and 4 until the entire array is read.

Program Memory Lock Bits

The two-level Program Lock system consists of 2 Lock

bits and a 32-byte Encryption Array which are used to

protect the program memory against software piracy.

Encryption Array :

Within the EPROM array are 32 bytes of Encryption

Array that are initially unprogrammed (all 1s). Every

time that a byte is addressed during a verify, address

lines are used to select a byte of the Encryption array.

This byte is then exclusive-NORed (XNOR) with the

code byte, creating an Encrypted Verify byte.

The algorithm, with the array in the unprogrammed

state (all 1s), will return the code in its original, un-

modified form. It is recommended that whenever the

Encryption Array is used, at least one of the Lock Bits

be programmed as well.

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