AN2014 datasheet(11/65 Pages) STMICROELECTRONICS

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DocID10701 Rev 10

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AN2014

EEPROM cell and memory array architecture

As EEPROM devices use a single supply voltage, the high voltage must be generated and

managed internally. A set of analog circuits is available to generate and control the high

voltage from the single external power supply:

•

voltage and current references to control oscillators and timings.

•

a regulated charge pump that generates a stable 15 to 18V voltage, HiV, from the

single external power supply.

•

a ramp generator that, from the stable HiV voltage, makes the specific waveform

(shown in Figure 8) that is to be applied to the cells.

VPP is the high voltage that is directly applied to the FLOTOX cell, as described earlier. The

precise shape of the VPP voltage waveform is critical, and has a direct effect on the reliability

and endurance of the memory cells. The slope, plate time and maximum level are

parameters that are very carefully controlled.

Writing new data in an EEPROM array triggers an auto-erase of all the addressed bytes,

resets them all to the Erased state, and then selectively programs those bits that should be

set to the Written state.

Figure 8. VPP signal applied to EEPROM cells

(HiV is the output of the charge pump)

To summarize: Binary information is coded by means of a FLOTOX transistor. The floating

gate is a reservoir filled with negative electric charges that modify its electrical

characteristics. The electric charges can be made to migrate into or out of the reservoir by

applying a high voltage to a thin Tunnel Oxide. The binary information is read by comparing

the cell (FLOTOX transistor) current to a reference.

AI10235

VPP

5ms

t(ms)

HiV

18V

Auto-Erase

Program

Write Cycle = Auto-Erase + Program

AN2014 Datenblatt(PDF) 11 Page - STMicroelectronics