AN2014 datasheet(13/65 Pages) STMICROELECTRONICS

13 / 65 page

DocID10701 Rev 10

13/65

AN2014

EEPROM cell and memory array architecture

1.2

Electrical architecture of ST serial EEPROM arrays

In the previous section, the EEPROM functionality was considered at the single bit level.

We will now zoom out of the memory cell to the full EEPROM array, in order to give an

overview of the architecture of an EEPROM device.

1.2.1

Memory array architecture

An EEPROM device is made of an array of memory cells whose organization allows byte

granularity, the automatic erasing of the addressed bytes (Erased state), and the

programming of only those bits that are to be changed to ‘1’ (Written state). The array (as

shown in Figure 10) is organized as follows:

•

Each memory cell consists of one Select transistor in series with a FLOTOX transistor

and each byte is made up of eight memory cells and a Control Gate transistor with a

drain that is common to the Control Gates of all eight FLOTOX transistors.

•

Rows (in the horizontal direction) are made up of 16 bytes (or more, depending on the

memory size (the number of bytes within each row being a function of the array size).

For each row, all Select transistors and all Control Gate transistors are connected to

the Row line.

•

Columns are grouped by eight bit-lines plus one Cg-line. This is then repeated as many

times as the number of bytes in a row.

•

A bit-line is common to all the drains of the Select transistors of each memory cell

located in the column. A Cg-line is common to all the sources of the Control Gate

transistors of the column.

Figure 10. Architecture of the memory array (showing the grouping in bytes)

Note:

Figure 10 corresponds to a memory array without ECC (Error Correction Code) logic (see

Section 5.5: Cycling endurance and data retention and AN2440 for more details).

Cg-Line 0

8 Bit-Line Latches

8 Select

transistors

8 FLOTOX

transistors

Row-

Line 0

b07

b06

b00

Cg-Line i

8 Bit-Line Latches

bi7

bi6

bi0

Control

Gate

transistor

Row-

Line n

AI10224b

Column 0

Column i

Byte

Select

transistor

FLOTOX

transistor

Memory Cell

AN2014 Datenblatt(PDF) 13 Page - STMicroelectronics

AN2014 Datenblatt(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datenblatt Download

Link URL