Z8018233FSC datasheet(80/109 Pages) ZILOG

80 / 109 page

3-80

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

ABSOLUTE MAXIMUM RATINGS

Voltage on V

CC with respect to VSS ........... –0.3V to +7.0V

Voltages on all inputs

with respect to V

SS ........................... –0.3V to VCC +0.3V

Operating Ambient Temperature ................... 0 to +70

°C

Storage Temperature ............................ –55

°C to +150°C

STANDARD TEST CONDITIONS

The DC Characteristics and capacitance sections below

apply for the following standard test conditions, unless

otherwise noted. All voltages are referenced to GND (0V).

Positive current flows into the referenced pin (Figure 89).

Available operating temperature range is:

S = 0

°C to +70°C

Voltage Supply Range:

+4.50V

≤ V

CC ≤ + 5.50V Z80182

+3.0V

≤ V

CC ≤ + 3.60V Z8L182

All AC parameters assume a load capacitance of 100 pF.

Add 10 ns delay for each 50 pF increase in load up to a

maximum of 150 pF for the data bus and 100 pF for

address and control lines. AC timing measurements are

referenced to 1.5 volts (except for clock, which is referenced

to the 10% and 90% points). Maximum capacitive load for

CLK is 125 pF.

Note: The ESCC™ Core is only guaranteed to operate at 20

MHz 5.0 volts or 10 MHz 3.3 volts. Upon reset, the Z182

system clock is "divided by one" before clocking the

ESCC. When Z182 is operated above 20 MHz 5.0 volts or

10 MHz 3.3 volts, the ESCC should be programmed to

"divide-by-two" mode.

Stresses greater than those listed under Absolute Maximum

Ratings may cause permanent damage to the device. This

is a stress rating only; operation of the device at any

condition above those indicated in the operational sections

of these specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

+5V

From Output

Under Test

100 pF

250

µA

2.1 k

Ω

Figure 89. Test Load Diagram

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