Z8018233FSC datasheet(47/109 Pages) ZILOG

47 / 109 page

3-47

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

When the part is in IDLE mode, the clock oscillator is kept

oscillating, but the clock to the rest of the internal circuit,

including the CLKOUT, is stopped completely. IDLE mode

is exited in a similar way as STANDBY mode, i.e., RESET,

BUS REQUEST or EXTERNAL INTERRUPTS, except that

the 217 bit wake-up timer is bypassed; all control signals are

asserted eight clock cycles after the exit conditions are

gathered.

STANDBY-QUICK RECOVERY Mode

STANDBY-QUICK RECOVERY mode is an option offered

in STANDBY mode to reduce the clock recovery time in

STANDBY mode from 217 clock cycles (6.5 ms at 20 MHz)

to 26 clock cycles (3.2

µs at 20 MHz). This feature can only

be used when providing an oscillator as clock source.

To enter STANDBY-QUICK RECOVERY mode:

1. Set D6 and D3 to 1 and 1, respectively.

2. Set the I/O STOP bit (D5 of ICR,

I/O Address = 3FH) to 1.

3. Execute the SLEEP instruction.

When the part is in STANDBY-QUICK RECOVERY mode,

the operation is identical to STANDBY mode except when

exit conditions are gathered, i.e., RESET, BUS REQUEST

or EXTERNAL INTERRUPTS; the clock and other control

signals are recovered sooner than the STANDBY mode.

Note: If STANDBY-QUICK RECOVERY is enabled, the

user must make sure stable oscillation is obtained within

64 clock cycles.

CPU Control Register

The Z8S180 has an additional register which allows the

programmer to select options that directly affect the CPU

performance as well as controlling the STANDBY operating

mode of the chip. The CPU Control Register (CCR) allows

the programmer to change the divide-by-two internal clock

to divide-by-one. In addition, applications where EMI noise

is a problem, the Z8S180 can reduce the output drivers on

selected groups of pins to 25% of normal pad driver

capability which minimizes the EMI noise generated by the

part.

LNCPUCTL

0 = Standard Drive

1 = 25% Drive On CPU

Control Signals

CPU Control Register (CCR) Addr 1FH

LNAD/DATA

0 = Standard Drive

1 = 25% Drive On

A19-A0, D7-D0

Reserved

Standby/Idle Enable

00 = No Standby

01 = Idle After Sleep

10 = Standby After Sleep

11 = Standby After Sleep

64 Cycle Exit

(Quick Recovery)

LNPHI

0 = Standard Drive

1 = 25% Drive On

EXT.PHI Clock

BREXT

0 = Ignore BUSREQ

In Standby/Idle

1 = Standby/Idle Exit

on BUSREQ

Clock Divide

0 = XTAL/2

1 = XTAL/1

00000000

Figure 51. CPU Control Register

Z8018233FSC Datenblatt(PDF) 47 Page - Zilog, Inc.

Z8018233FSC Datenblatt(HTML) 47 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL