Z8018233FSC datasheet(74/109 Pages) ZILOG

74 / 109 page

3-74

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

16550 MIMIC REGISTERS (Continued)

Modem Status Register

Bit 7 Data Carrier Detect

This bit must be written by the Z180 MPU.

Bit 6 Ring Indicator

This bit must be written by the Z180 MPU.

Bit 5 Data Set Ready

This bit must be written by the Z180 MPU.

Bit 4 Clear to Send

This bit must be written by the Z180™ MPU.

Bit 3 Delta Data Carrier Detect

This bit is set to 1 whenever the Data Carrier Detect bit

changes state. This bit is reset when the PC/XT/AT reads

the Modem Status Register.

Bit 2 Trailing Edge Ring Indicator

This bit is set to 1 on the falling edge of the Ring Indicator

bit. This bit is reset when the PC/XT/AT reads the Modem

Status Register.

Bit 1 Delta Data Set Ready

This bit is set to 1 whenever the Data Set Ready bit

changes state. This bit is reset when the PC/XT/AT reads

the Modem Status Register.

Bit 0 Delta Clear To Send

This bit is set to 1 whenever the Clear To Send bit changes

state. This bit is reset when the PC/XT/AT reads the Modem

Status Register.

000000

Divisor Latch (LS)

Figure 79. Scratch Register

(PC Read/Write, Address 07H)

(Z180 MPU Read Only, Address xxF7H)

Scratch Register

Bits 7-0 Scratch Register

This register is used by the PC/XT/AT programmer for

temporary data storage. The Z180 MPU is able to read this

to the Z180 MPU is generated.

000000

Divisor Latch (MS)

Figure 80. Divisor Latch (LS)

(PC Read/Write, Address 00H and DLAB=1)

(Z180 MPU Read Only, Address xxF8H)

Divisor Latch (LS)

Bit 7-0 Divisor Latch Most Significant Byte (MS)

This register contains the Low order byte of the Baud rate

divisor. Writing to this register with the PC/XT/AT will

generate an interrupt to the Z180 MPU. It can then read the

Baud rate divisor and set up the application.

000000

Scratch Register

Figure 81. Divisor Latch (MS)

(PC Read/Write, Address 01H and DLAB=1)

(Z180 MPU Read Only, Address xxF9H)

Divisor Latch (MS)

Bit 7-0 Divisor Latch Most Significant Byte (MS)

This register contains the High order byte of the Baud rate

divisor. Writing to this register with the PC/XT/AT will

generate an interrupt to the Z180 MPU. It can then read the

Baud rate divisor and set up the application.

Z8018233FSC Datenblatt(PDF) 74 Page - Zilog, Inc.

Z8018233FSC Datenblatt(HTML) 74 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL