USB3503 datasheet(37/73 Pages) MICROCHIP

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DS00001584B-page 37

USB3503

6.3

I2C Message format

6.3.1

SEQUENTIAL ACCESS WRITES

The I2C interface will support sequential writing of the register address space of the USB3503. This mode is useful for

configuring contiguous blocks of registers. Please see section on SOC interface for address definitions. Figure 6-2

shows the format of the sequential write operation. Where color is visible in the figure, blue indicates signaling from the

I2C master, and gray indicates signaling from the USB3503 slave:

In this operation, following the 7-bit slave address, an 8-bit register address is written indicating the start address for

sequential write operation. Every data access after that is a data write to a data register where the register address incre-

ments after each access and ACK from the slave must occur. Sequential write access is terminated by a Stop condition.

6.3.2

SEQUENTIAL ACCESS READS

The I2C interface will support direct reading of the USB3503 registers. In order to read one or more register addresses,

the starting address must be set by using a write sequence followed by a read. The read register interface supports

auto-increment mode. The master should send a NACK instead of an ACK when the last byte has been transferred.

In this operation, following the 7-bit slave address, 8-bit register address is written indicating the start address for

sequential read operation to be followed. In the read sequence, every data access is a data read from a data register

where the register address increments after each access. Write sequence can end with optional Stop (P). If so the Read

sequence must start with a Start (S) otherwise it must start with Repeated Start (Sr).

Figure 6-3 shows the format of the read operation. Where color is visible in the figure, blue and gold indicate signaling

from the I2C master, and gray indicates signaling from the USB3503 slave.

FIGURE 6-2:

I2C SEQUENTIAL ACCESS WRITE FORMAT

FIGURE 6-3:

SEQUENTIAL ACCESS READ FORMAT

7-Bit Slave Address

nnnnnnnn

Data value for

XXXXXX

...

nnnnnnnn

Data value for

XXXXXX + y

xxxxxxxx

Address

(bits 7-0)

7 - B i t S l a v e

A ddr es s

xx xx xx xx

Re g i s t e r

A d dr es s

( b i t s

7- 0)

O p t i ona l . I f pr es ent , N e x t

ac c e s s

m u s t hav e

S t ar t ( S ) ,

o t he r w i s e

R epe at S t a r t ( S r )

7- B i t S l av e A ddr es s

n n n n n n n n

AC K

R egi s t er v a l ue

f o r xx xxx xxx

n n n n n n n n

AC K

R egi s t er v a l u e

f o r xx xxx xxx + 1

...

n n n n n n n n

NA C K

I f pr ev i ous w r i t e s e t t i ng up

R e g i s t er addr es s end ed w i t h a

S t o p ( P ) , o t h e r w i s e it w ill b e

R e p eat ed S t a r t ( S r )

R egi s t er v a l ue

f o r xxx xxx xx + y

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