ADC14X250 datasheet(53/69 Pages) TI1

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ADC14X250

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SLASE49 – DECEMBER 2015

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The SYSREF frequency for a continuous SYSREF signal can be the indicated frequency fLMFC or integer sub-harmonic such as fLMFC /

2, fLMFC / 3, and so forth. Gapped-periodic SYSREF signals should have pulses spaced by the associated periods 1 / fLMFC, 2 / fLMFC, 3 /

fLMFC, and so forth.

6. Configure the SYSREF driver into its idle state.

9.1.4.2 Link Interruption

The internal frame and multi-frame clocks must be stable to maintain the JESD204B link. The ADC14X250 is

designed to maintain the JESD204B link in most conditions but some features interrupt the internal clocks and

break the link.

The following actions cause a break in the JESD204B link:

•

The ADC14X250 device is configured into power-down mode or sleep mode

•

The ADC14X250 device CLKIN clock divider setting is changed

•

The serial data receiver performs a synchronization request

•

The ADC14X250 device detects a SYSREF assertion that is not aligned with the internal frame or multi-frame

clocks

•

The CLKIN input is interrupted

•

Power to the device is interrupted

The following actions do not cause a change in clock alignment nor break the JESD204B link:

•

The ambient temperature or operating voltages are varied across the ranges specified in the normal operating

conditions.

•

The ADC14X250 device detects a SYSREF assertion that is aligned with the internal frame and multi-frame

clocks.

9.1.4.3 Clock Configuration Examples

The features provided in the ADC14X250 device allow for a number of clock and JESD204B link configurations.

These examples in Table 26 show some common implementations and may be used as a starting point for a

more customized implementation.

Table 26. Example ADC14X250 Clock Configurations

Parameter

Example 1

Example 2

Example 3

CLKIN Frequency

250 MHz

1000 MHz

2000 MHz

CLKIN Divider

Sampling Rate

250 MSPS

K (Frames per Multi-

frame)

LMFC Frequency

12.5 MHz

7.8125 MHz

15.625 MHz

SYSREF

Frequency(1)

12.5 MHz

7.8125 MHz

15.625 MHz

Serial Bit Rate

5.0 Gb/s

9.1.4.4 Configuring the JESD204B Receiver

The ASIC or FPGA device that receives the JESD204B data from the ADC14X250 device must be configured

properly to interpret the serial stream. Table 4 describes the JESD204B parameter information transmitted during

the ILA sequence and may be used to dynamically configure the receiving device. Due to the various

arrangements of output data across different operational modes, some parameters (N, N’, CS, CF) do not always

reflect the data properties in all modes. Therefore, the ILA information does not completely describe the data

output from the ADC14X250 device in all modes.

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