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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADC14X250 Datenblatt(PDF) 14 Page - Texas Instruments |
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ADC14X250 Datenblatt(HTML) 14 Page - Texas Instruments |
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14 / 69 page  VI + VI - VIS VID GND VID = |VI + ± VI -| VIS = |VI + + V I -| / 2 VI - VSS dVSS/dt VI + VI + referenced to V I - VSS = 2*|VI + ± VI -| VI + and V I - referenced to GND 14 ADC14X250 SLASE49 – DECEMBER 2015 www.ti.com Product Folder Links: ADC14X250 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Timing Requirements (continued) Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS. VSPI = 1.8 V (1). Typical values are at T A = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tH-SYNCb SYNCb assertion hold time Required SYNCb hold time after assertion before de-assertion to initiate a link re-synchronization. 4 Frame clock cycles tILA ILA duration Duration of the ILA sequence . 4 Multi-frame clock cycles SERIAL OUTPUT DATA TIMING CHARACTERISTICS FSR Serial bit rate 1.0 5.0 Gb/s UI Unit Interval 5.0 Gb/s Data Rate 200 ps tR, tF Edge transition rise and fall times 40 ps DJ Deterministic jitter Includes periodic jitter (PJ), data dependent jitter (DDJ), duty cycle distortion (DCD), and inter-symbol interference (ISI); 5.0 Gb/s data rate. 0.032 p-p UI 6.33 p-p ps RJ Random jitter Assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate 0.118 p-p UI 1.48 rms ps TJ Total jitter Sum of DJ and RJ. Assumes BER of 1e-15 (measured Q = 15.6); 5.0 Gb/s data rate. 0.148 p-p UI 29.56 p-p ps SPI BUS TIMING CHARACTERISTICS (1) fSCLK Serial clock frequency fSCLK = 1 / tP 20 MHz tPH SCLK pulse width – high 10 ns tPL SCLK pulse width – low 10 ns tSSU SDI input data setup time 5 ns tSH SDI input data hold time 5 ns tODZ SDO output data driven-to-3-state time 15 ns tOZD SDO output data 3-state-to-driven time 15 ns tOD SDO output data delay time 20 ns tCSS CSB setup time 5 ns tCSH CSB hold time 5 ns tIAG Inter-access gap Minimum time CSB must be de-asserted between accesses 5 ns Figure 1. Electrical Level Diagram for Differential Input Signals |
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