SPEAR320S datasheet(62/113 Pages) STMICROELECTRONICS

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Pin description

SPEAr320S

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Doc ID 022508 Rev 2

Table 31.

Ethernet signals description

Signal name

Description

Dir.

PL_GPIO_# /

ball number

Configuration mode

(see Section 3.4.2)

MII0

MII0_COL

PHY collision

This signal is asserted by the PHY when

a collision is detected on the medium.

This signal is not synchronous to any

clock.

(Active high)

PL_GPIO_13/A1

Alternate function

MII0_CRS

PHY CRS

This signal is asserted by the PHY when

either the transmit or receive medium is

not idle. The PHY deasserts this signal

when both transmit and receive medium

are idle. This signal is not synchronous to

any clock. (Active high)

PL_GPIO_12/D4

Alternate function

MII0_MDC

Management data clock

The MAC provides timing reference for

the MAC_MDIO signal through this

aperiodic clock. The maximum frequency

of this clock is 2.5 MHz.This clock is

generated from the application clock

(HCLK) via a clock divider.

PL_GPIO_11/E5

Alternate function

MII0_MDIO

Management data input/output

PL_GPIO_10/C3

Alternate function

MII0_RXCLK

Reception clock

This is the reception clock (25/2.5 MHz in

100M/10Mbps) provided by the external

PHY for MII interfaces. The MII0_RXDn

signals that the Ethernet controller

receives are synchronous to this clock.

PL_GPIO_20/B4

Alternate function

MII0_RXD0

PHY receive data

These bits provide the MII receive data

nibble. The validity of the data is qualified

with MII0_RXDV and MII0_RXER.

PL_GPIO_17/C4

Alternate function

MII0_RXD1

PL_GPIO_16/E6

Alternate function

MII0_RXD2

PL_GPIO_15/B3

Alternate function

MII0_RXD3

PL_GPIO_14/A2

Alternate function

MII0_RXDV

PHY receive data valid

When high, indicates that the data on the

MII0_RXDn bus is valid. It remains

asserted continuously from the first

recovered byte/nibble of the frame

through the final recovered byte/nibble.

PL_GPIO_19/A3

Alternate function

MII0_RXER

PHY receive error

When high, indicates an error or carrier

extension in the received frame on the

MII0_RXDn bus.

PL_GPIO_18/D5

Alternate function

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