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SPEAR320S Datenblatt(PDF) 84 Page - STMicroelectronics |
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SPEAR320S Datenblatt(HTML) 84 Page - STMicroelectronics |
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84 / 113 page ![]() Timing requirements SPEAr320S 84/113 Doc ID 022508 Rev 2 Note: Values in Table 57 refer to the common internal source clock which has a period of tHCLK = 6 ns. Figure 15. EMI read cycle waveform without acknowledgement on EMI_WAIT Note: The values of tSE, tENr, tDCS, tSCS are programmable via the EMI registers. Figure 16. EMI write cycle waveform without acknowledgement on EMI_WAIT Note: The values of tSE, tENw, tDCS, tSCS are programmable via the EMI registers. Table 57. EMI timing requirements for write cycle with acknowledgement on WAIT Symbol Min tCS->Wait tHCLK tWAIT 4*tHCLK EMI_A# EMI_BYTEN# EMI_D# EMI_CEn# EMI_OE Address Byte Enable Data tSE tSCS tENr tDCS EMI_A# EMI_BYTEN# EMI_D# EMI_CEn# EMI_WE Write Data Byte Enable Data tSE tSCS tENw tDCS |
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