CC1020-RTR1 datasheet(14/95 Pages) TI1

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CC1020

SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015

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4.9

Frequency Synthesizer

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical

specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V,

fC = 14.7456 MHz if nothing else stated.

PARAMETER

TYP

UNIT

CONDITION

At 12.5 kHz offset from carrier

–90

dBc/Hz

Unmodulated carrier.

At 25 kHz offset from carrier

–100

dBc/Hz

Phase noise,

Measured using loop filter components

402 to 470 MHz

At 50 kHz offset from carrier

–105

dBc/Hz

given in Table 6-2. The phase noise will

12.5 kHz channel spacing

be higher for larger PLL loop filter

At 100 kHz offset from carrier

–110

dBc/Hz

bandwidth.

At 1 MHz offset from carrier

–114

dBc/Hz

At 12.5 kHz offset from carrier

–85

dBc/Hz

Unmodulated carrier.

At 25 kHz offset from carrier

–95

dBc/Hz

Phase noise,

Measured using loop filter components

804 to 960 MHz

At 50 kHz offset from carrier

–101

dBc/Hz

given in Table 6-2. The phase noise will

25 kHz channel spacing

be higher for larger PLL loop filter

At 100 kHz offset from carrier

–109

dBc/Hz

bandwidth.

At 1 MHz offset from carrier

–118

dBc/Hz

12.5 kHz channel spacing, 433 MHz

2.7

kHz

After PLL and VCO calibration. The PLL

PLL loop bandwidth

loop bandwidth is programmable.

25 kHz channel spacing, 868 MHz

8.3

kHz

12.5 kHz channel spacing, 433 MHz

900

µs

307.2 kHz frequency step to RF frequency

within ±10% of channel spacing. Depends

25 kHz channel spacing, 868 MHz

640

µs

PLL lock time

on loop filter component values and

(RX / TX turn time)

PLL_BW register setting. See Table 5-13

500 kHz channel spacing

µs

for more details.

12.5 kHz channel spacing, 433 MHz

3.2

Time from writing to registers to RF

PLL turn-on time.

frequency within ±10% of channel

25 kHz channel spacing, 868 MHz

2.5

From power down mode

spacing. Depends on loop filter

with crystal oscillator

component values and PLL_BW register

500 kHz channel spacing

700

µs

running.

setting. See Table 5-12 for more details.

Specifications

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