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ADE3700SX Datenblatt(PDF) 56 Page - STMicroelectronics

Teilenummer ADE3700SX
Bauteilbeschribung  Analog LCD Display Engine for XGA and SXGA Resolutions
PDF  89 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ADE3700SX Datenblatt(HTML) 56 Page - STMicroelectronics

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Pattern Generator
ADE3700
56/89
PGEN_GRID3
0x0604
R/W
[7:0]
0x0
Grid Row 3
PGEN_GRID4
0x0605
R/W
[7:0]
0x0
Grid Row 4
PGEN_GRID5
0x0606
R/W
[7:0]
0x0
Grid Row 5
PGEN_GRID6
0x0607
R/W
[7:0]
0x0
Grid Row 6
PGEN_GRID7
0x0608
R/W
[7:0]
0x0
Grid Row 7
PGEN_GRID_X_L
0x0609
R/W
[7:0]
0x0
width of a grid block in pixels [7:0]
PGEN_GRID_X_H
0x060A
[7:4]
Reserved
R/W
[3:0]
0x0
width of a grid block in pixels [11:8]
PGEN_GRID_Y_L
0x060B
R/W
[7:0]
0x0
height of a grid block in pixels [7:0]
PGEN_GRID_Y_H
0x060C
[7:4]
Reserved
R/W
[3:0]
0x0
height of a grid block in pixels [11:8]
PGEN_GRID_X_OFFSET_X_L
0x060D
R/W
[7:0]
0x0
grid block horizontal offset in pixels [7:0]
PGEN_GRID_X_OFFSET_X_H
0x060E
[7:4]
Reserved
R/W
[3:0]
0x0
Grid Block Horizontal Offset in pixels [11:8]
PGEN_GRID_Y_OFFSET_Y_L
0x060F
R/W
[7:4]
0x0
Grid Block Vertical Offset in pixels
PGEN_GRID_Y_OFFSET_Y_H
0x0610
R/W
[3:0]
PGEN_P0_MODE
0x0611
R/W
Pattern 0 Control
R/W
[7:5]
0x0
number of bars in C0
R/W
[4:2]
0x0
number of bars in C1
R/W
[1]
0x0
0: pattern continues to progress across
block boundaries
1: block boundaries cause the pattern to
restart
R/W
[0]
0x0
0: normal mode
1: C0 = video bypass
PGEN_P1_MODE
0x0612
Pattern 1 Control
R/W
[7:5]
0x0
number of bars in C0
R/W
[4:2]
0x0
number of bars in C1
R/W
[1]
0x0
0: pattern continues to progress across
block boundaries
1: block boundaries cause the pattern to
restart
R/W
[0]
0x0
0: normal mode
1: C0 = video bypass
PGEN_P0_WIDTH_X_L
0x0613
R/W
[7:0]
0x0
Pattern 0 Bar Width [7:0]
PGEN_P0_WIDTH_X_H
0x0614
[7:4]
Reserved
R/W
[3:0]
0x0
Pattern 0 Bar Width [11:8]
PGEN_P0_WIDTH_X_OFFSET_L
0x0615
R/W
[7:0]
0x0
Pattern 0 Horizontal Offset [7:0]
Table 19: PGEN Registers (Sheet 2 of 5)
Register Name
Addr
Mode
Bits
Default
Description



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