ADS5500IPAPR datasheet(21/29 Pages) TI

21 / 29 page

ADS5500

SBAS303C − DECEMBER 2003 − REVISED MARCH 2004

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5500 is a low-power, 14-bit, 125MSPS,

CMOS, switched capacitor, pipeline ADC that operates

from a single 3.3V supply. The conversion process is

initiated by a falling edge of the external input clock.

Once the signal is captured by the input S&H, the input

sample is sequentially converted by a series of small

resolution stages, with the outputs combined in a digital

correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through

the pipeline every half clock cycle. This process results

in a data latency of 16.5 clock cycles, after which the

output data is available as a 14-bit parallel word, coded

in either straight offset binary or binary two’s

complement format.

INPUT CONFIGURATION

The analog input for the ADS5500 consists of a

differential sample-and-hold architecture implemented

using a switched capacitor technique, shown in

Figure 4.

1,L2 : 6nh to 10nh effective

1a,R1b :25Ω to 35Ω

1a,C1b : 2.2pF to 2.6pF

1,CP2 : 2.5pF to 3.5pF

3,CP4, : 1.2pF to 1.8pF

ACROSS : 0.8pF to 1.2pF

3 :80Ω to 120Ω

Switches:

All switches are on in sample phase.

Approximately half of every clock period is a sample phase.

1a,W1b : On Resistance: 25Ω to 35Ω

2 : On Resistance: 7.5Ω to 15Ω

3a,W3b : On Resistance: 40Ω to 60Ω

1a,W1b,W2,W3a,W3b : Off Resistance: 1e10

ACROSS

SAMPLE

PHASE

SAMPLE

PHASE

SWITCH

SAMPLE

PHASE

VINCM

SAMPLE

PHASE

SAMPLE

PHASE

INP

INM

Figure 4. Analog Input Stage

ADS5500IPAPR Datenblatt(PDF) 21 Page - Texas Instruments

ADS5500IPAPR Datenblatt(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datenblatt Download

Link URL