ADS5500IPAPR datasheet(25/29 Pages) TI

25 / 29 page

ADS5500

SBAS303C − DECEMBER 2003 − REVISED MARCH 2004

www.ti.com

0.01

µF

CLKP

ADS5500

CLKM

0.01

µF

Differential Square Wave

or Sine Wave

(3V

PP)

Figure 11. AC-Coupled, Differential Clock Input

For high input frequency sampling, it is recommended

to use a clock source with very low jitter. Additionally,

the internal ADC core uses both edges of the clock for

the conversion process. This means that, ideally, a 50%

duty cycle should be provided. Figure 12 shows the

performance variation of the ADC versus clock duty

cycle.

SFDR

SNR

Clock Duty Cycle (%)

S =125MSPS

IN =20MHz

Figure 12. AC Performance vs Clock Duty Cycle

Bandpass filtering of the source can help produce a

50% duty cycle clock and reduce the effect of jitter.

When using a sinusoidal clock, the clock jitter will further

improve as the amplitude is increased. In that sense,

using a differential clock allows for the use of larger

amplitudes without exceeding the supply rails and

absolute maximum ratings of the ADC clock input.

Figure 13 shows the performance variation of the

device versus input clock amplitude. For detailed

clocking schemes based on transformer or PECL-level

clocks, refer to the ADS5500EVM User’s Guide

(SLWU010), available for download from www.ti.com.

AC PERFORMANCE vs CLOCK AMPLITUDE

Differential Clock Amplitude (V)

S =125MSPS

IN =70MHz

0.5

1.0

1.5

2.0

2.5

3.0

SFDR

SNR

Figure 13. AC Performance vs Clock Amplitude

INTERNAL DLL

In order to obtain the fastest sampling rates achievable

with the ADS5500, the device uses an internal digital

phase lock loop (DLL). Nevertheless, the limited

frequency range of operation of DLL degrades the

performance at clock frequencies below 60MSPS. In

order to operate the device below 60MSPS, the internal

DLL must be shut off using the DLL OFF mode

described in the Serial Interface Programming section.

The

Typical

Performance

Curves

show

the

performance obtained in both modes of operation: DLL

ON (default), and DLL OFF. In either of the two modes,

the device will enter power down mode if no clock or

slow clock is provided. The limit of the clock frequency

where the device will function properly is ensured to be

over 10MHz.

ADS5500IPAPR Datenblatt(PDF) 25 Page - Texas Instruments

ADS5500IPAPR Datenblatt(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datenblatt Download

Link URL