ADS5500IPAPR datasheet(24/29 Pages) TI

24 / 29 page

ADS5500

SBAS303C − DECEMBER 2003 − REVISED MARCH 2004

www.ti.com

POWER SUPPLY SEQUENCE

The ADS5500 requires a power-up sequence where the

DRVDD supply must be at least 0.4V by the time the

AVDD supply reaches 3.0V. Powering up both supplies

at the same time will work without any problem. If this

sequence is not followed, the device may stay in

power-down mode.

POWER DOWN

The device will enter power-down in one of two ways:

either by reducing the clock speed to between DC and

1MHz, or by setting a bit through the serial

programming interface. Using the reduced clock speed,

the power-down may be initiated for clock frequencies

below 10MHz. For clock frequencies between 1MHz

and 10Mhz, this can vary from device to device, but will

power-down for clock speeds below 1MHz.

The device can be powered down by programming the

internal register (see Serial Programming Interface

section). The outputs become tri-stated and only the

internal reference is powered up to shorten the

power-up time. The Power-Down mode reduces power

dissipation to a minimum of 180mW.

REFERENCE CIRCUIT

The

ADS5500

has

built-in

internal

reference

generation, requiring no external circuitry on the printed

circuit board (PCB). For optimum performance, it is best

to connect both REFP and REFM to ground with a 1

µF

decoupling capacitor in series with a 1

Ω resistor, as

shown in Figure 8. In addition, an external 56.2k

Ω

resistor should be connected from IREF (pin 31) to

AGND to set the proper current for the operation of the

ADC, as shown in Figure 8. No capacitor should be

connected between pin 31 and ground; only the 56.2k

Ω

resistor should be used.

REFP

REFM

IREF

56k

Ω

µF

Ω

Figure 8. REFP, REFM, and IREF Connections for

Optimum Performance

CLOCK INPUT

The ADS5500 clock input can be driven with either a

differential clock signal or a single-ended clock input,

with little or no difference in performance between both

configurations. The common-mode voltage of the clock

inputs is set internally to CM (pin 17) using internal 5k

Ω

resistors that connect CLKP (pin 10) and CLKM (pin 11)

to CM (pin 17), as shown in Figure 9.

Ω

CLKM

CLKP

6pF

3pF

Figure 9. Clock Inputs

When driven with a single-ended CMOS clock input, it

is best to connect CLKM (pin 11) to ground with a

0.01

µF capacitor, while CLKP is AC-coupled with a

0.01

µF capacitor to the clock source, as shown in

Figure 10.

0.01

µF

0.01

µF

CLKP

ADS5500

CLKM

Square Wave

or Sine Wave

(3V

PP)

Figure 10. AC-Coupled, Single-Ended Clock Input

The ADS5500 clock input can also be driven

differentially, reducing susceptibility to common-mode

noise. In this case, it is best to connect both clock inputs

to the differential input clock signal with 0.01

µF

capacitors, as shown in Figure 11.

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