LDO

2.8V

BATTERY

100 nF

100 nF

4.7 PH

10 PF

10 PF

R1

G1

B1

R2

G2

B2

10 nF

10 nF

10 nF

ASE

AD2

AD1

LP3950

SINGLE ENDED

AUDIO SIGNAL

DIFFERENTIAL

AUDIO SIGNAL

SW

FB

GND_BOOST

EN

BOOST

RT

RT

82k

100 nF

ADC

MICROCONTROLLER

100 nF

LEVEL SHIFTER

SPI

I

2

C

RGB PATTERN

GENERATOR

AGC

OSC

THSD

PWM

CTRL

AMPL

FREQ

GND_RGB

GNDA

100 nF

D1

LP3950

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

www.ti.com

Block Diagram

Figure 2. LP3950 Block Diagram

Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values. RESET is entered always if

input NRST is LOW or internal Power On Reset is active.

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is

the low power consumption mode, when all the circuit functions are disabled. Registers can be written in

this mode and the control bits are effective immediately after start up.

To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine.

Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal

shutdown event is present.

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the

boost output is raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB

outputs are off during the 10 ms delay to ensure smooth startup. The Boost startup is entered from

Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written

HIGH.

NORMAL: During the NORMAL mode the user controls the chip using the control registers. Registers can be

written in any sequence and any number of bits can be altered in a register within one write cycle . If the

default mode is selected, default control register values are used.

6

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