LP3950SLSLASHNOPB datasheet(12/38 Pages) TI1

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SDA

SCL

ack from slave

start

msb Chip Address lsb

SCL

ack from slave

msb Register Add lsb

msb

DATA

lsb

stop

ack from slave

ack from master

repeated start

data from slave

SDA

start

Id = 36h

w ack

addr = K¶00

ack

r ack

$GGUHVV K¶00 data

ack stop

msb Chip Address lsb

Id = 36h

LP3950

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

www.ti.com

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

Figure 10 .

Figure 10. I2C Read Cycle

Figure 11. I2C Timing Diagram

Table 2. I2C Timing Parameters(1)

Symbol

Parameter

Limit

Units

Min

Max

Hold Time (repeated) START Condition

0.6

µs

Clock Low Time (1.65V

≤ VDDIO < 1.80V)

3.2

µs

Clock Low Time (1.80V

≤ VDDIO ≤ VDD1,2V)

1.3

µs

Clock High Time (1.65V

≤ VDDIO < 1.80V)

1200

Clock High Time (1.80V

≤ VDDIO ≤ VDD1,2V)

600

Setup Time for a Repeated START Condition

600

Data Hold Time (data output, delay generated by LP3950)

300

900

Data Hold Time (data input)

900

Data Setup Time

100

Rise Time of SDA and SCL

20+0.1Cb

300

Fall Time of SDA and SCL

15+0.1Cb

300

Set-up Time for STOP condition

600

Bus Free Time between a STOP and a START Condition

1.3

µs

Capacitive Load Parameter for Each Bus Line.

200

Load of One Picofarad Corresponds to One Nanosecond.

(1)

Data guaranteed by design

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