start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

Id = 36h

w

ack

addr = 02h

ack

ack

DGGUHVV K¶02 data

stop

ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

0

1

1

0

1

1

0

C SLAVE address (chip address)

I

2

SDA

SCL

S

P

STO

LP3950

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SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

signal transition from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transition

master can generate repeated START conditions. First START and repeated START conditions are equivalent,

function-wise.

Figure 7. Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

eighth bit which is a data direction bit (R/W). The LP3950 address is 50'h or 51'h. The selection of the address is

“1” indicates a READ. The second byte selects the register to which the data will be written. The third byte

contains data to write to the selected register.

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = chip address, 50'h or 51'h for LP3950.

Copyright © 2004–2013, Texas Instruments Incorporated

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