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SC1200 Datenblatt(PDF) 46 Page - Texas Instruments

Teilenummer SC1200
Bauteilbeschribung  Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory
PDF  60 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SC1200 Datenblatt(HTML) 46 Page - Texas Instruments

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MSC1200
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SBAS289E
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ADC Offset Calibration Register Middle Byte (OCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D2H
00H
OCM
ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC
bits 7-0
offset calibration. A value which is written to this location will set the ADC offset calibration value.
ADC Offset Calibration Register High Byte (OCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D3H
MSB
00H
OCH
ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the
bits 7-0
ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
Program Status Word (PSW)
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow
bit 7
(during subtraction). Otherwise it is cleared to 0 by all arithmetic operations.
AC
Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition),
bit 6
or a borrow (during substraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic
operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0
Register Bank Select 1-0. These bits select which register bank is addressed during register accesses.
bits 4-3
OV
Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow
bit 2
(subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and
bit 0
cleared to 0 on even parity.
ADC Offset Calibration Register Low Byte (OCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D0H
CY
AC
F0
RS1
RS0
OV
F1
P
00H
RS1
RS0
REGISTER BANK
ADDRESS
00
0
00H-07H
01
1
08H-0FH
10
2
10H-17H
11
3
18H-1FH
OCL
ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the
bits 7-0
ADC offset calibration. A value which is written to this location will set the ADC offset calibration value.
7
6
5
4
3
2
1
0
Reset Value
SFR D1H
LSB
00H



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