SC1200 datasheet(38/60 Pages) TI

38 / 60 page

MSC1200

SBAS289E

www.ti.com

SPI Control (SPICON) (SERSEL bit determines SPICON control)

SBIT3-0

Serial Bit Count. Number of bits transferred (read only).

bits 7-4

SBIT3:0

COUNT

0x00

0x01

0x03

0x02

0x06

0x07

0x05

0x04

0x0C

Reset Value

SFR 9AH

SBIT3

SBIT2

SBIT1

SBIT0

ORDER

CPHA

ESS

CPOL

00H

ORDER

Set Bit Order for Transmit and Receive.

bit 3

0: Most Significant Bits First

1: Least Significant Bits First

CPHA

Serial Clock Phase Control.

bit 2

0: Valid data starting from half SCK period before the first edge of SCK

1: Valid data starting from the first edge of SCK

ESS

Enable Slave Select.

bit 1

0: SS (P1.4) is configured as a general-purpose I/O (default).

1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is high-

impedance when SS is high.

CPOL

Serial Clock Polarity.

bit 0

0: SCK idle at logic LOW

1: SCK idle at logic HIGH

Reset Value

SFR 9AH

SBIT3

SBIT2

SBIT1

SBIT0

STOP

START

DCS

CNTSEL

00H

I2C Control (I2CCON) (SERSEL bit determines I2CCON control)

SBIT3-0

Serial Bit Count. Number of bits transferred (read only).

bits 7-4

SBIT3:0

COUNT

0x00

0x01

0x03

0x02

0x06

0x07

0x05

0x04

0x0C

STOP

Stop-Bit Status.

bit 3

0: No Stop

1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA)

START

Start-Bit Status.

bit 2

0: No Stop

1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA)

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