Assertion no.

Description

Keysight PCI

Express

SigTest

Transmitter tests

PHY.3.1#26

DC common mode voltage

Y

N

PHY.3.2#1

De-emphasis on multiple bits same polarity in

succession

Y

N

PHY.3.2#2

Transition bit voltage

Y

N

PHY.3.3#1

Transmitter eye diagram

Y

N

PHY.3.3#2

Unit interval without SSC variations

Y

N

PHY.3.3#3

Minimum D+/D- output rise/fall time

Y

N

PHY.3.3#4

Jitter median to max deviation

Y

N

PHY.3.3#5

Maximum RMS AC common mode voltage

Y

N

PHY.3.3#9

Minimum eye width

Y

N

Receiver tests

PHY.3.4#1

Minimum receiver eye diagram

N

PHY.3.4#2

AC peak common mode input voltage

N

PHY.3.4#6

Jitter median to max deviation input

N

System board (connector) tests

EM.4#4

Minimum jitter

Y

Y

EM.4#20

Transmitter path eye diagram

Y

Y

Reference clock (connector) tests

PHY.3.3#2

Phase jitter

Y

PHY.3.3#1

Rising edge rate

Y

N/A

PHY.3.3#1

Falling edge rate

Y

N/A

PHY.3.3#4

Differential input high voltage

Y

N/A

PHY.3.3#4

Differential input low voltage

Y

N/A

PHY.3.3#9

Average clock period

Y

N/A

PHY.3.2#2

Duty cycle

Y

N/A

Add-in card (connector) tests

EM.4#13

Minimum jitter

Y

Y

EM.4#19

Transmitter path eye diagram

Y

Y

1. Receiver tests provided by the Keysight PCI Express software are listed under the PCIe 1.x or 2.0 test tabs

do not validate the receiver’s tolerance or ability to correctly receive data. They validate the signal at the

receiver against specified tolerances.

Tests Performed

The PCI Express electrical performance

validation and compliance software

performs the following tests as per

the PCI Express 1.0a and 1.1 electrical

specifications for add-in cards and

motherboard systems as documented

in Section 4 of the base specification

(“PHY”) and Section 4 of the card

electromechanical specification (“EM”).

For reference, the tests performed by the

SigTest application are also noted.

For Gen2 testing coverage, the

PCI-SIG decided not to create checklist,

as was done for Gen1. For test coverage

refer to section 4.7.2. Table 4-8 of the

PCI Express 2.0 Card Electromechanical

Specification.

For PCI Express 3.0, test coverage

includes items listed on table 4-18 under

section 4.3.3 of the PCI Express 3.0 Base

Specification.