LAN9116 datasheet(21/109 Pages) MICROCHIP

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DS00002268A-page 21

LAN9116

Then the Function looks in the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case

of a break in the 16 address repetitions, the PMT Function scans for the 48'hFF_FF_FF_FF_FF_FF pattern again in the

incoming frame.

The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will

also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a

node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame.

Destination Address Source Address ……………FF FF FF FF FF FF

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

…CRC

It should be noted that Magic Packet detection can be performed when LAN9116 is in the D0 or D1 power states. In the

D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as

well as wake-up frame detection, are automatically enabled when the device enters the D1 state.

3.6

32-bit vs. 16-bit Host Bus Width Operation

The LAN9116 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus. An external strap

is used to select between the two modes. 32-bit mode is the native environment for the LAN9116 Ethernet controller

and no special requirements exist for communication in this mode. However, when this part is used in the 16-bit mode,

two writes or reads must be performed back to back to properly communicate.

The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the “Hardware Configuration Reg-

ister”. Please refer to Section 5.3.9, "HW_CFG—Hardware Configuration Register," on page 61 for additional informa-

tion on this register.

3.6.1

16-BIT BUS WRITES

The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This

DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit

write). No ordering requirements exist. The processor can access either the low or high word first, as long as the next

write is performed to the other word. If a write to the same word is performed, the LAN9116 disregards the transfer.

3.6.2

16-BIT BUS READS

The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This

DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit

read). No ordering requirements exist. The processor can access either the low or high word first, as long as the next

read is performed from the other word. If a read to the same word is performed, the data read is invalid and should be

re-read. This is not a fatal error. The LAN9116 will reset its read counters and restart a new cycle on the next read. The

Upper 16 data pins (D[31:16]) are not driven by the LAN9116 in 16-bit mode. These pins have internal pull-down’s and

the signals are left in a high-impedance state.

3.7

Big and Little Endian Support

The Microchip LAN9116 supports “Big-” or “Little-Endian” processors in either 16 or 32-bit bus width modes. To support

big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes. In addition, for a 16-bit

interface, the WORD_SWAP—Word Swap Control must be set correctly following Table 3-7, "Byte Lane Mapping".

The host bus interface can be selected via an external strap to translate the data bus into either mode. Please refer to

Table 2-4, “Serial EEPROM Interface Signals,” on page 10, for information on multiplexed signal D32/nD16 for more

information on data bus width selection.

Additionally, please refer to Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 68 for additional informa-

tion on status indication on Endian modes.

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